Intel (Quantum Computing) — vendor dossier

Intel (Quantum Computing)

Quantum computers
I

Silicon spin-qubit quantum computing research program inside Intel Labs, scoped to Intel's Quantum Computing group (Components Research / Intel Labs). The strategic bet is fab-compatibility — electron-spin qubits encoded in CMOS-style silicon quantum dots, fabricated on Intel's 300-mm production lines at D1 (Hillsboro) using EUV lithography and the same transistor flow as logic chips, paired with cryogenic CMOS control (Horse Ridge) to collapse the room-temperature control rack. Research-stage, not yet a commercial product line; the current flagship Tunnel Falls is distributed to academic partners under the LPS Qubit Collaboratory. Long-running QuTech (TU Delft / TNO) partnership since 2015.

HQ
Hillsboro, Oregon, USA
Founded
1968
Status
public
Last verified
Sun May 24 2026 08:00:00 GMT+0800 (Singapore Standard Time)

Timeline

201520162017201820192020202120222023202420252026202720282029today
2015-09
Intel announces $50M, 10-year collaboration with QuTech (TU Delft + TNO) on quantum computing
2019-12
Horse Ridge I cryogenic control chip announced (first-generation cryo-CMOS controller)
2020-12
Horse Ridge II cryogenic CMOS control chip unveiled — 22nm FinFET, verified at 4 K, adds qubit readout and gate-potential control
2022-04
Intel-QuTech Nature Electronics paper — silicon qubits fabricated in industrial 300-mm CMOS line
2022-06
Intel Quantum SDK 1.0 released — full-stack software for silicon spin qubits with C++ programming model
2023-06
Tunnel Falls 12-qubit silicon spin-qubit research chip released to academic partners (LPS, Sandia, U. Maryland, U. Rochester, U. Wisconsin-Madison)
2024-03
Intel and QuTech report first qubits made in industrial 300-mm semiconductor manufacturing facilities
2024-05
Nature paper — "Probing single electrons across 300-mm spin qubit wafers"; 99.9% single-qubit gate fidelity reported on all-CMOS fabrication
late-2020s
2D arrays with increased qubit count and connectivity; high-fidelity two-qubit gates on industrial CMOS line
Founded 1968 shipped milestone public roadmap

Current flagship

Tunnel Falls — 12-qubit silicon spin-qubit research chip (300-mm CMOS, D1 Hillsboro)

Milestones

  1. 2024-05
    Nature paper — "Probing single electrons across 300-mm spin qubit wafers"; 99.9% single-qubit gate fidelity reported on all-CMOS fabrication
    Quantum computers paper source ↗
  2. 2024-03
    Intel and QuTech report first qubits made in industrial 300-mm semiconductor manufacturing facilities
    Quantum computers press source ↗
  3. 2023-06
    Tunnel Falls 12-qubit silicon spin-qubit research chip released to academic partners (LPS, Sandia, U. Maryland, U. Rochester, U. Wisconsin-Madison)
    Quantum computers press source ↗
  4. 2022-06
    Intel Quantum SDK 1.0 released — full-stack software for silicon spin qubits with C++ programming model
    Quantum computers blog source ↗
  5. 2022-04
    Intel-QuTech Nature Electronics paper — silicon qubits fabricated in industrial 300-mm CMOS line
    Quantum computers paper source ↗
  6. 2020-12
    Horse Ridge II cryogenic CMOS control chip unveiled — 22nm FinFET, verified at 4 K, adds qubit readout and gate-potential control
    Quantum computers press source ↗
  7. 2019-12
    Horse Ridge I cryogenic control chip announced (first-generation cryo-CMOS controller)
    Quantum computers press source ↗
  8. 2015-09
    Intel announces $50M, 10-year collaboration with QuTech (TU Delft + TNO) on quantum computing
    Quantum computers press source ↗

Roadmap

  • late-2020s 2D arrays with increased qubit count and connectivity; high-fidelity two-qubit gates on industrial CMOS line source ↗
  • undated Million-qubit-class silicon spin-qubit systems leveraging Intel's 300-mm manufacturing scale (no firm date — Intel publicly avoids hype timelines) source ↗

Capability details

Quantum computing

Qubit type
spin-si
Physical qubits
12
Logical qubits
0
1Q gate fidelity
0.999
2Q gate fidelity
—
T₁
—
T₂
—
EC code
—
Connectivity
nearest-neighbour
13 unverified fields
  • modalities.qc.two_q_fidelity
  • modalities.qc.coherence_t1_ms
  • modalities.qc.coherence_t2_ms
  • modalities.qc.ec_code
  • modalities.qc.gate_set
  • modalities.qc.one_q_fidelity — 99.9% headline figure from Neyens et al. Nature 2024 — wafer-scale CMOS-process result, not the device-best
  • modalities.qc.physical_qubits_current — 12 reflects Tunnel Falls (the chip distributed to academic partners); Intel has not publicly disclosed a larger successor device as of May 2026
  • key_personnel.0.since
  • key_personnel.1.since
  • key_personnel.2 — Duplicate of Jim Clarke pending confirmation of separate Senior Principal Engineer role; may be removed on next refresh
  • shareholders — Intel Corp. (NASDAQ:INTC) institutional stakes from 13F aggregators; Intel Quantum is not a separate legal entity so quantum-specific ownership does not apply
  • roadmap.0.target
  • roadmap.1.target

People

  • Jim Clarke — Director, Quantum Hardware (Intel Labs) (since 2012) ↗
  • Anne Matsuura — Director, Quantum & Molecular Technologies (Intel Labs) (since 2017) ↗
  • James S. Clarke — Senior Principal Engineer, Quantum Computing (since 2015) ↗
  • Lip-Bu Tan — CEO, Intel Corporation (since 2025-03) ↗
  • Sachin Katti — Chief Technology Officer, Intel (since 2025) ↗

References